1. Field of the Invention
The present invention relates to a semiconductor device having an element isolation structure by the STI (Shallow Trench Isolation) method and a method of manufacturing the same.
2. Description of the Related Art
Conventionally, as an element isolation structure, an element isolation structure formed by the STI method (hereinafter, simply referred to as an STI element isolation structure) has been used in which insulation within an active region is ensured by embedding an insulation material in a groove formed within the element isolation region. This STI element isolation structure is expected to contribute to demands for miniaturization of semiconductor devices in recent years because it can ensure element isolation unlike a field oxide film or the like protruding from the substrate surface formed by a so-called LOCOS method.
(Patent Document 1) Japanese Patent Application Laid-open No. 2000-22141
(Patent Document 2) Japanese Patent Application Laid-open No. 2004-55640
(Non-Patent Document 1) Y. Kumagai et al., “Evaluation of change in drain current due to strain in 0.13-μm-node MOSFETs”, SSDM, pp. 14-15, 2003.